1. Field of the Invention
This invention relates generally to digital to analog converters (DACs), and more specifically, to a circuit which improves the accuracy of DACs by reducing the unwanted change in the output voltage of the DAC by minimizing the variation in analog ground current flowing through extraneous package, lead and contact resistances.
2. Description of the Prior Art
Shown in FIG. 1 is a block diagram of a conventional 16-bit monolithic DAC. A 16-bit control line is divided into most significant bits (MSB) and least significant bits (LSB). The three MSBs are coupled to individual current switches 11 and current sources 13 (in FIG. 2), which are referenced generally by block 10. The thirteen LSBs are also coupled to current switches and current sources, which are referenced generally by the block 14. The three MSB current switches and current sources 10 may be comprised of three binary weighted current sources which are each coupled to a current switch. Alternatively, the MSB current switches and current sources 10 may be comprised of seven equally weighted current sources which are switched on and off in combinations to provide the required output which corresponds to having a particular code on the three most significant bit control lines. There are commonly known advantages to both methods of implementing the MSB current switches and current sources, and the choice of which to incorporate into a DAC is dependant upon the desires of the circuit designer.
The LSB current sources are all weighted equally, and are coupled to a R-2R resistance ladder 16 through the current switches. The resistance ladder 16 divides the LSB current sources into binary weights which are summed with the weighted output of the MSB current switches 10 at output summing point 18. The MSB and LSB current sources 10 and 14, respectively, are biased by a voltage reference circuit 12. Finally, in a conventional DAC, an output amplifier 20 converts the output current I.sub.o at summing point 18 to an output voltage V.sub.o at its output 22.
Thus, a conventional 16-bit DAC receives a 16-bit digital signal and converts each bit of the signal into a corresponding current weight which is summed and converted into an analog output voltage.
Shown in FIG. 2 is a more detailed circuit representation of a MSB current switch and current source referenced earlier as block 10. For clarity, the block 10A has been subdivided into a current switch 11 and a current source 13.
The current switch 11 is a single-pole double-throw type comprised of a differential pair of transistors 24 and 26. The emitters of transistors 24 and 26 are coupled together and to the current source 13. The base of each transistor is controlled by the appropriate line of the 16-bit digital input signal at inputs 1A and 1B. Transistor 24 is henceforth called the "ON" transistor, and transistor 26 is called the "OFF" transistor. The collector of transistor 24 is coupled to the summing junction 18. The collector of transistor 26 is usually coupled to ground. The other side of the current source 13 is conventionally coupled to the negative supply -V.sub.s. Referring to 10A as a general guideline for any particular bit, the following happens when a particular bit is turned on in a conventional DAC. Signals will be applied at 1A and 1B of 10A which are generated from the appropriate bit control line, so that "ON" transistor 24 will be turned on and "OFF" transistor 26 will be turned off. The current I.sub.w will originate at the positive supply +V.sub.s, flow through the internal circuitry of the operational amplifier 20, then from the op amps output terminal 20A, through the feedback resistor 28, through the "ON" transistor 24 and current source 13, and finally to the negative supply -V.sub.s. The value of the weighted current I.sub.w of the specific bit will appear at the summing junction 18 and as an output voltage V.sub.o (which is equal to the product of feedback resistor 28 and I.sub.w) at the output 22 of amplifier 20. It will appear as the product because the voltage differential between the negative and positive inputs to the amplifier 20 will be zero, with the value of the voltage at the inputs being held to that of analog ground (the positive input).
Problems in conventional DACs arise when a particular bit is in a turned off mode (i.e. transistor 24 off and transistor 26 on). When a particular bit of the DAC is not on, transistor 26 is biased on and current flows from analog ground, through transistor 26 and current source 13, to -V.sub.s. Thus, the value of the weighted current, I.sub.w, does not appear at the summing junction 18. However, when a bit is switched from an on to an off mode, a contribution by that bit to the current in analog ground 30 appears where there was previously not one. The changing value of the current flowing in analog ground 30 results in undesirable voltage errors at the output 22 of the DAC, when extraneous impedance 34 exists in analog ground as shown in FIG. 3.
The equation in FIG. 3 demonstrates the effect of changing analog ground currents and the need to keep the magnitude of the analog ground current below a defined maximum amount, and also to keep analog ground current changes (when the bits are switched) below a maximum value. The 16-bit DAC is represented by block 32. The output of the DAC 32 is shown at node 22 and represented by V.sub.o. The analog circuit ground of the DAC is shown at node 30 with the current symbol I.sub.gnd representing the current which flows through the analog ground. In a usual application, whether at a testing or packaging stage by the manufacture, or being used by the customer, there will be a system ground 36 and some extraneous wiring, contact or packaging impedance 34, labeled Z.sub.ext. The effect of an analog ground circuit I.sub.gnd is to alter the ideal voltage output of the DAC 32 by the amount equal to the product of I.sub.gnd and Z.sub.ext, where V.sub.DAC (represented by a battery 32A) is the desired ideal output voltage of the DAC. Thus, the output voltage V.sub.o of the DAC 32 contains an error value of the ideal DAC output voltage V.sub.DAC node 22.
In conventional DACs, the error voltage (I.sub.gnd .times.Z.sub.ext) varied as I.sub.gnd varied as explained above. A varying error voltage limited accurate use of the DAC. Wiring inductance caused time dependent error voltages which resulted in extended time before the DAC output would settle to its final value. Thus, there existed a need to design a DAC which would reduce and hold the analog ground current constant below a maximum value as the digital input values changed.